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1 memory all data sheets are subject to change without notice (619) 503-3300 - fax: (619) 503-3301 - www.maxwell.com 16 megabit (512k x 32-bit) 89c1632 ?2001 maxwell technologies. all rights reserved. mcm sram 12.20.01 rev 1 1000558 f eatures : ? four 512k x 8 sram architecture ?r ad -p ak ? technology hardens against natural space radia- tion technology ? total dose hardness: - > 100 krad (si), depending upon space mission ? excellent single event effects: - sel > 68 mev/mg/cm 2 - seu threshold = 3 mev/mg/cm 2 - seu saturated cross section: 6e-9 cm 2 /bit ? package: 68-pin quad flat package ? fast access time: 20, 25 and 30 ns ? completely static memory - no clock or timing strobe required ? internal bypass capacitor ? high-speed silicon-gate cmos technology ? 5v or 3v 10% power supply ? equal address and chip enable access times ? three-state outputs ? all inputs and outputs are ttl compatible d escription : maxwell technologies? 89c1632 high-performance 16 mega- bit multi-chip module (mcm) static random access memory features a greater than 100 krad (si) total dose tolerance, depending upon space mission. t he four 4-megabyte sram die and bypass capacitors are inco rporated into a high-reliable hermetic quad flat-pack cerami c package. with high-perfor- mance silicon-gate cmos technology, the 89c1632 reduces power consumption and eliminates the need for external clocks or timing strobes. it is equipped with output enable (oe ) and four byte enable (cs1 - cs4 ) inputs to allow greater system flexibility. when oe input is high, the output is forced to high impedance. maxwell technologies' patented r ad -p ak ? packaging technol- ogy incorporates radiation shie lding in the microcircuit pack- age. in a geo orbit, r ad -p ak provides true greater than 100 krad (si) total radiation dose tolerance, dependent upon space mission. it eliminates the need fo r box shielding while provid- ing the required radiation shieldin g for a lifetime in orbit or a space mission. this product is av ailable in class h or class k packaging and screening. cs 1-4 mcm oe, we address 4mb sram 4mb sram 4mb sram 4mb sram power ground i/o 0-7 i/o 8-15 i/o 16-23 i/o 24-31 16 megabit (512k x 32-bit) sram mcm logic diagram
memory 2 all data sheets are subject to change without notice ?2001 maxwell technologies. all rights reserved. 16 megabit (512k x 32-bit) mcm sram 89c1632 12.20.01 rev 1 1000558 t able 1. p inout d escription p in s ymbol d escription 34-28, 42-36, 62-64, 7, 8 a0-a18 address enable 65 we writeenable 66 oe output enable 3-6 cs1 - cs4 chip enable 43-46, 48-56, 58-61, 9-12, 14-17, 19-22, 24-27 i/o0-i/o31 data input/output 2, 67, 68 nc no connection 1, 18, 35, 52 v cc +5v power supply 13, 23, 47, 57 v ss ground t able 2. 89c1632 a bsolute m aximum r atings (v oltage referenced to v ss = 0v) p arameter s ymbol m in m ax u nits power supply voltage relative to v ss v cc -0.5 +7.0 v voltage relative to v ss for any pin except v cc v in , v out -0.5 v cc +0.5 v power dissipation p d -- 4.0 w operating temperature t a -55 +125 c storage temperature t s -65 +150 c t able 3. 89c1632 r ecommended o perating c onditions (v cc = 5.0 + 10%, t a = -55 to +125 c, unless otherwise noted ) p arameter s ymbol m in m ax u nits supply voltage, (operating voltage range) v cc 4.5 5.5 v input high voltage v ih 2.2 v cc + 0.5 (1) 1. v ih (max) = v cc + 2v ac (pulse width < 10ns) for i < 80 ma. v input low voltage v il -0.5 (2) 2. v il (min) = -2.0v ac; (pulse width < 20 ns) for i < 80 ma. 0.8 v
memory 3 all data sheets are subject to change without notice ?2001 maxwell technologies. all rights reserved. 16 megabit (512k x 32-bit) mcm sram 89c1632 12.20.01 rev 1 1000558 t able 4. 89c1632 c apacitance (f = 1.0 mh z , dv = 3.0v, t a = 25 c) p arameter s ymbol t est c onditions m ax u nits input capacitance 1 cs1 - cs4 , oe , we i/o0-7, i/o8-15, i/o16-23, i/o24-31 1. guaranteed by design. c in v in = 0 v 7 28 7 pf input / output capacitance 1 c out v i/o = 0 v 8 pf t able 5. 89c1632 dc e lectrical c haracteristics (v cc = 5.0 + 10%, t a = -55 to +125 c, unless otherwise noted ) p arameter s ymbol t est c onditions m in t yp m ax u nits input leakage current i li v in = 0 to v cc -8.0 -- +8.0 ua output leakage current i lo cs = v ih , v out = v ss to v cc -8.0 -- +8.0 ua average operating current cycle time: 20 ns 25 ns 30 ns i cc min. cycle, 100% duty, cs = v il , i out = 0 ma v in = v ih or v il -- -- -- -- 800 760 720 ma standby power supply current i sb cs = v ih , cycle time > 25ns -- -- 240 ma cmos standby power supply current i sb1 cs > v cc - 0.2v, f = 0 mhz, v in > v cc - 0.2v or v in < 0.2v -- -- 60 ma output low voltage v ol i ol = + 8.0 ma -- -- 0.4 v output high voltage v oh i oh = -4.0 ma 2.4 -- -- v t able 6. 89c1632 ac o perating c onditions and c haracteristics (v cc = 5.0 + 10%, t a = -55 to +125 c, unless otherwise noted ) p arameter m in t yp m ax u nits input pulse level 0.0 -- 3.0 v output timing measurement reference level -- -- 1.5 v input rise/fall time -- -- 3.0 ns input timing measurement reference level -- -- 1.5 v
memory 4 all data sheets are subject to change without notice ?2001 maxwell technologies. all rights reserved. 16 megabit (512k x 32-bit) mcm sram 89c1632 12.20.01 rev 1 1000558 t able 7. 89c1632 r ead c ycle (v cc = 5.0 + 10%, t a = -55 to +125 c, unless otherwise noted ) p arameter s ymbol m in t yp m ax u nits read cycle time -20 -25 -30 t rc 20 25 30 -- -- -- -- -- -- ns address access time -20 -25 -30 t aa -- -- -- -- -- -- 20 25 30 ns chip select to output -20 -25 -30 t co -- -- -- -- -- -- 20 25 30 ns output enable to output -20 -25 -30 t oe -- -- -- -- -- -- 10 12 14 ns output enable to low-z output -20 -25 -30 t olz -- -- -- 0 0 0 -- -- -- ns chip enable to low-z output -20 -25 -30 t lz -- -- -- 3 3 3 -- -- -- ns output disable to high-z output -20 -25 -30 t ohz -- -- -- 5 6 8 -- -- -- ns chip disable to high-z output -20 -25 -30 t hz -- -- -- 5 6 8 -- -- -- ns output hold from address change -20 -25 -30 t oh 3 3 3 -- -- -- -- -- -- ns t able 8. 89c1632 f unctional d escription cs we oe m ode i/o p in s upply c urrent hx 1 x 1 not select high-z i sb , i sb1
memory 5 all data sheets are subject to change without notice ?2001 maxwell technologies. all rights reserved. 16 megabit (512k x 32-bit) mcm sram 89c1632 12.20.01 rev 1 1000558 l h h output disable high-z i cc l h l read d out i cc llx 1 write d in i cc 1. x = don?t care. t able 9. 89c1632 w rite c ycle (v cc = 5.0 + 10%, t a = -55 to +125 c, unless otherwise noted ) p arameter s ymbol m in t yp m ax u nits write cycle time -20 -25 -30 t wc 20 25 30 -- -- -- ns chip select to end of write -20 -25 -30 t cw 14 17 20 -- -- -- ns address set-up time -20 -25 -30 t as 0 0 0 -- -- -- ns address valid to end of write -20 -25 -30 t aw 14 17 20 -- -- -- ns write pulse width (oe high) -20 -25 -30 t wp 14 17 20 -- -- -- ns write pulse width (oe low) -20 -25 -30 t wp1 20 25 30 -- -- -- ns write recovery time -20 -25 -30 t wr 0 0 0 -- -- -- ns write to output high-z -20 -25 -30 t whz -- -- -- 5 7 9 -- -- -- ns t able 8. 89c1632 f unctional d escription cs we oe m ode i/o p in s upply c urrent
memory 6 all data sheets are subject to change without notice ?2001 maxwell technologies. all rights reserved. 16 megabit (512k x 32-bit) mcm sram 89c1632 12.20.01 rev 1 1000558 data to write time overlap -25 -30 t dw 10 12 14 -- -- -- ns data hold from write time -20 -25 -30 t dh 0 0 0 -- -- -- ns end write to output low-z -20 -25 -30 t ow -- -- -- 3 3 3 -- -- -- ns t able 9. 89c1632 w rite c ycle (v cc = 5.0 + 10%, t a = -55 to +125 c, unless otherwise noted ) p arameter s ymbol m in t yp m ax u nits
memory 7 all data sheets are subject to change without notice ?2001 maxwell technologies. all rights reserved. 16 megabit (512k x 32-bit) mcm sram 89c1632 12.20.01 rev 1 1000558 f igure 1. ac t est l oads f igure 2. t iming w aveform of r ead c ycle (1) (a ddress c ontrolled ) f igure 3. t iming w aveform of r ead c ycle (2) (we = v ih ) 1. we is high for read cycle. 2. all read cycle timing is referenced from the la st valid address to the first transition address.
memory 8 all data sheets are subject to change without notice ?2001 maxwell technologies. all rights reserved. 16 megabit (512k x 32-bit) mcm sram 89c1632 12.20.01 rev 1 1000558 3. t hz and t ohz are defined as the time at which the outputs achiev e the open circuit condition and are not referenced to v oh or v ol levels. 4. at any given temperature and voltage conditions, t hz (max) is less than t lz (min) both for a given device and from device to device. 5. transition is measured + 200mv from steady state voltage with load(b). th is parameter is sampled and not 100% tested. 6. device is continuously selected with cs = v il . 7. address valid prior to coincident with cs transition low. 8. for common i/o applications, minimization or elimination of bus contention condi tions is necessary during read and write cycle. f igure 4. t iming w aveform of w rite c ycle (1) (oe c lock ) f igure 5. t iming w aveform of w rite c ycle (2) (oe l ow f iixed )
memory 9 all data sheets are subject to change without notice ?2001 maxwell technologies. all rights reserved. 16 megabit (512k x 32-bit) mcm sram 89c1632 12.20.01 rev 1 1000558 f igure 6. t iming w aveform of w rite c ycle (3) (cs c ontrolled ) 1. all write cycle timing is referenced from the la st valid address to the first transition address. 2. a write occurs during the overlap of a low cs and we . a write begins at the latest transition cs going low and we going low. a write ends at the earliest transition cs going high or w e going high. t wp is measured from the begi nning of write to the end of write. 3. t cw is measured from the later of cs going low to end of write. 4. t as is measured from the address valid to the beginning of write. 5. t wr is measured from the end of write to the address change. t wr applied in case a write ends as cs or we going high. 6. if oe , cs and we are in the read mode during this period, the i/o pins are in the output low-z state. inputs of opposite phase of the output must not be applied because bus contention can occur. 7. for common i/o applications, minimization of elimination of bus contention condi tions is necessary during read and write cycle. 8. if cs foes low simultaneously with we going or after we going low, the outputs remain high impedance state. 9. d out is the read data of the new address. 10.when cs is low, i/o pins are in the output state. the input signals in the opposite phase leading to the output should not be applied.
memory 10 all data sheets are subject to change without notice ?2001 maxwell technologies. all rights reserved. 16 megabit (512k x 32-bit) mcm sram 89c1632 12.20.01 rev 1 1000558 f igure 7. sram h eavy i on c ross s ection f igure 8. sram p roton seu c ross s ection s tatic
memory 11 all data sheets are subject to change without notice ?2001 maxwell technologies. all rights reserved. 16 megabit (512k x 32-bit) mcm sram 89c1632 12.20.01 rev 1 1000558 q68-04 note: all dimensions in inches 68 p in r ad -p ak ? q uad f lat p ackage s ymbol d imension m in n om m ax a 0.206 0.225 0.244 b 0.015 0.017 0.018 c 0.008 0.009 0.12 d 1.479 1.494 1.509 d1 0.800 e 0.050 bsc s1 -- 0.339 -- f1 1.239 1.244 1.249 f2 1.429 1.434 1.439 l 2.485 2.510 2.545 l1 2.485 2.500 2.505 l2 1.690 1.700 1.710 a1 0.180 0.195 0.210 n68
memory 12 all data sheets are subject to change without notice ?2001 maxwell technologies. all rights reserved. 16 megabit (512k x 32-bit) mcm sram 89c1632 12.20.01 rev 1 1000558 important notice: these data sheets are created using the chip manufacturer s published specifications. maxwell technologies verifies functionality by testing key parameters either by 100% testing, sample test ing or characterization. the specifications presented within these data sheets represent the latest and most accurate information available to date. however, these specifications are subject to change without notice and maxwell technologies assumes no responsibility for the us e of this information. maxwell technologies? products are not authorized for use as critical components in li fe support devices or systems without express written approval from maxwell technologies. any claim against maxwell technologies must be made within 90 days from the date of shipment from maxwell tech- nologies. maxwell technologies? liability shall be limited to replacement of defective parts.
memory 13 all data sheets are subject to change without notice ?2001 maxwell technologies. all rights reserved. 16 megabit (512k x 32-bit) mcm sram 89c1632 12.20.01 rev 1 1000558 product ordering options model number feature option details 89c1632 rp q x -xx access time screening flow package radiation feature base product nomenclature 20 = 20 ns 25 = 25 ns 30 = 30 ns multi chip module (mcm) k = maxwell class k h = maxwell class h e = engineering (testing @ +25c ) i = industrial (testing @ -55c, +25c, +125c) q = quad flat pack rp = r ad -p ak ? package 16 megabit (512k x 32-bit) mcm sram

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